Video signals may be transmitted by cable, microwave, telephone systems, fiber optic, infrared, etc. for satellite, television, VCR, and other video capture equipment and applications. Conventional video equipment generates a composite video signal that includes synchronizing and video information in one signal. As shown in FIG. 1A, a composite video signal comprises a synchronization pulse or sync tip, a front porch including a color burst, and a back porch or pedestal. Characteristically, video signals have a built in synchronization or sync pulse to enable the video signal instrumentation to synchronize the signal such that it is shifted to a particular DC level. The sync pulse is repeated for each scan line of an image and has an undetermined DC level. Since, in many applications, only one power supply is used, the signal level entering the system must be above the ground level. Therefore, a clamping circuit is needed to clamp the lowest level of the video signal to a certain DC level to fully recover the incoming video signal. Illustrated in FIG. 1b is a known clamp pulse generated for a clamping circuit which is used to clamp onto the lowest level of the video signal shown in FIG. 1a. For many applications, clamping automatically must be performed in the analog domain such that the sync pulse is clamped. Thereafter, a separate clamping circuit is used to clamp the voltage at the pedestal, front porch or any other user-defined level.
FIG. 2 illustrates a typical application wherein an analog video signal is applied to the input pin 201 of the video processing integrated circuit 200 through an clamping capacitor or AC coupling capacitor 202. To enable the video signal to be processed, a clamping circuit 204 is used to establish a signal reference level of the incoming video signal to the dynamic input range of the video processing circuit 206. In other words, a DC reference is provided for the filtered video signal so that the ADC 206 outputs a digital word representing zero when the level of the filtered video signal is at its lowest point; thus, maximum headroom and consistent signal processing are provided. In other words, the DC value of the bottom level of the sync pulse is such that the output of the ADC 206 is equal to a digital zero level output code. This level shifted signal can then be processed by a digital signal processor DSP 208 to produce a digital output. Optionally, a digital to analog converter 210 may supply an analog output. As a result, the analog input video signal will not be distorted or clipped due to the DC offset of the input being out of range with the input dynamic range of the ADC 206. Furthermore, the level shifted signal needs to refer to a known value independent of the DC offset of the video signal input.
A known clamping circuit 300 as shown in FIG. 3, as is disclosed in U.S. Pat. No. 5,986,719 which is incorporated by reference herein, input 302 connects to clamping capacitor 304. Clamping capacitor 304 couples to a clamping node 306. Clamping node 306 connects to diode 308 which couples between the voltage reference Vref and clamping node 206. Finally a buffer 310 having a gain A couples to the clamping node 306. In operation, when the sync pulse pulls the voltage at node 306 low, diode 308 turns on and maintains the voltage level of node 204 equal to the reference voltage Vref minus the base-emitter voltage Vbe where base-emitter voltage Vbe is the p-n junction voltage drop across diode 308 when it is on. Reference voltage Vref is set such that A*(Vref−Vbe) is equal to the zero reference digital level of an analog to digital converter (ADC, not shown) coupled to buffer 310. At the end of the sync pulse, the positive-going edge turns diode 308 off and node 306 floats in response to the filtered input video signal. Unless the voltage at node 306 is less than the reference voltage Vref prior to clamping, proper clamping will not occur. Another disadvantage is that a leakage current associated with diode 308 causes the DC level to drop during the horizontal scan of a video signal. Even though the purpose of the leakage current is to ensure that the voltage at node 306 is lower than the reference voltage Vref, the leakage current tends to differ from diode to diode; thereby affecting the accuracy of any connecting ADC (not shown).
Another approach incorporates the use of a feedback loop and are disclosed in U.S. Pat. Nos. 5,995,166 and 5,986,719 which are incorporated by reference herein. When utilizing feedback loops, however, the system must rely on shorting the output of an amplifier with the clamp reference level output to the clamping capacitor, which requires high power consumption due to the amplifier and causes instability and settling issues.
There still exists a need for a clamping circuit having two modes of operation which include both a bottom level and mid-level clamping mode. Furthermore, the clamping circuit must eliminate the use of a feedback loop. The clamping circuit must be able to correct the DC level without causing line noise. Also for low voltage single power supply applications, the clamping circuit needs to allow maximum dynamic range to the input. This clamping circuit must eliminate the need for a voltage reference circuit such that the reference voltage may be as low as ground. Moreover, the clamping circuit must provide a consistent supply of leakage current and; thereby, increase reliability.